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pace1750a single chip, 15mhz to 40mhz, cmos 16-bit processor features implements the mil-std-1750a instruction set architecture single chip pace technology tm cmos 16-bit processor with 32 and 48-bit floating point arithmetic dais instruction mix execution performance including floating point arithmetic 1.3 mips at 20 mhz 1.9 mips at 30 mhz 2.6 mips at 40 mhz integer dais mix performance 3.9 mips at 40 mhz conventional integer processing mix performance 5.0 mips at 40 mhz instruction execution at 40 mhz over the military temperature range 0.10 sec integer add/sub 0.57 sec integer multiply 0.70 sec floating point add/sub 1.07 sec floating point multiply 15, 20, 30, and 40 mhz operation over the military temperature range extensive error and fault management and interrupt capability 24 user accessible registers single 5v 10% power supply power dissipation over military temperature range < 0.30 watts at 20 mhz < 0.35 watts at 30 mhz < 0.40 watts at 40 mhz ttl signal level compatible inputs and outputs multiprocessor and co-processor capability built-in function (bif) for user defined instructions two programmable timers available in: ? 64-pin dip or gull wing (50 mil pin centers) ? 68-pin pin grid array (pga) ? 68-lead quad pack (leaded chip carrier) general description the pace1750a is a general purpose, single chip, 16-bit cmos microprocessor designed for high performance floating point and integer arithmetic, with extensive real time environment support. it offers a variety of data types, including bits, bytes, 16-bit and 32-bit integers, and 32-bit and 48-bit floating point numbers. it provides 13 addressing modes, including direct, indirect, indexed, based, based indexed and immediate long and short, and it can access 2 mwords of segmented memory space (64 kwords segments). the pace1750a offers a well-rounded instruction set with 130 instruction types, including a comprehensive integer, floating point, integer-to-floating point and floating point-to-integer set, a variety of stack manipulation instructions, high level language support instructions such as compare between bounds and loop control instructions. it also offers some unique instructions such as vectored l/o, supports executive and user modes, and provides an escape mechanism which allows user-defined instructions using a coprocessor. the chip includes 16 general purpose registers, 8 other user-accessible registers, and an array of real time application support resources, such as 2 programmable timers, a complete interrupt controller supporting 16 levels of prioritized internal and external interrupts, and a faults and exceptions handler controlling internally and externally generated faults. the microprocessor achieves very high throughput of 2.6 mips for a standard real time integer/floating point instruction mix at a 40 mhz clock. it executes integer add in 0.1 s, integer multiply in 0.575 s, floating point add in 0.7 s, and floating point multiply in 1.075 s, for register operands at a 40 mhz clock speed. the pace1750a uses a single multiplexed 16-bit parallel bus. status signals are provided to determine whether the processor is in the memory or i/o bus cycle, reading and writing, and whether the bus cycle is for data or instructions. the basic bus cycle is 4 clocks long. the pace1750a will extend the cycle by insertion of wait states in the address and data phases (in response to rdya and rdyd signals, repectively) and will hold the machine in hi-z if this cpu has not acquired the bus. a typical non-bus cycle is three clocks long. however, variable length cycles are used for such repetitive operations as multiply, divide, scale and normalize, reducing significantly the number of cpu clocks per operation step and resulting in very fast integer and floating point execution times. document # micro-3 rev. c revised october 2005
page 2 of 24 pace1750a document # micro-3 rev. c absolute maximum ratings 1 supply voltage range -0.5v to 7.0v input voltage range storage temperature range input current range voltage applied to inputs current applied to outputs 3 maximum power dissipation 2 -0.5v to v cc + 0.5v -65c to + 150c -30ma to +5ma -0.5v to vcc + 0.5v 150 ma 1.5w operating worst case power dissipation (outputs open): device type 01 device type 02 device type 03 0.25w at 15 mhz 0.30w at 20 mhz 0.35w at 30 mhz lead temperature range (soldering 10 seconds) 300c thermal resistance, junction-to-case ( jc ), note 5: cases x and t cases y and u case z 8c/w 5c/w 6c/w recommended operating conditions supply voltage range 4.5v to 5.5v case operating temperature range -55c to +125c note 1: stresses above the absolute maximum rating may cause permanent damage to the device. extended operation at the maximum levels may degrade performance and affect reliability. note 2: must withstand the added power dissipation due to short circuit test e.g., i os note 3: duration one second or less. note 4: device type definitions from 5962-87665 smd: device type 01: 15 mhz device type 02: 20 mhz device type 03: 30 mhz device type 04: 40 mhz note 5: case definitions from 5962-87665 smd: case x: dual in-line case t: dual in-line with gull-wing leads case y: leaded chip carrier with gull-wing leads case u: leaded chip carrier with unformed leads case z: pin grid array device type 04 0.40w at 40 mhz
page 3 of 24 pace1750a document # micro-3 rev. c dc electrical specifications (over recommended operating conditions) symbol parameter min max unit conditions 1 v ih input high level voltage 2.0 v cc + 0.5 v v il input low level voltage 2 ?0.5 0.8 v v cd input clamp diode voltage ?1.2 v v cc = 4.5v, i in = ?18ma 2.4 v v cc = 4.5v i oh = ?8.0ma v cc ? 0.2 v v cc = 4.5v i oh = ?300a 0.5 v v cc = 4.5v i ol = 8.0ma 0.2 v v cc = 4.5v i ol = 300a input high level current, i ih1 except ib 0 ? ib 15 ,10av in = v cc , v cc = 5.5v bus busy , bus lock input high level current, i ih2 ib 0 ? ib 15 ,50av in = v cc , v cc = 5.5v bus busy , bus lock input low level current, i il1 except ib 0 ? ib 15 , ?10 a v in = gnd, v cc = 5.5v bus busy , bus lock input low level current, i il2 ib 0 ? ib 15 , ?50 a v in = gnd, v cc = 5.5v bus busy , bus lock i ozh output three-state current 50 a v out = 2.4v, v cc = 5.5v i ozl output three-state current ?50 a v out = 0.5v, v cc = 5.5v quiescent power supply v in < 0.2v or < v cc ? 0.2v, i ccqc current (cmos input 10 ma f = 0mhz, outputs open, levels) v cc = 5.5v quiescent power supply v in < 3.4v, f = 0mhz, i ccqt current (ttl input 50 ma outputs open, levels) v cc = 5.5v i ccd dynamic power 15 mhz 40 ma v in = 0v to v cc , tr = tf = 2.5 ns, supply current 20 mhz 50 ma outputs open, 30 mhz 60 ma v cc = 5.5v 40 mhz 70 ma i os output short circuit current 3 ?25 ma v out = gnd, v cc = 5.5v c in input capacitance 10 pf c out output capacitance 15 pf c i/o bi-directional capacitance 15 pf notes 1. 4.5v v cc 5.5v, ?55c t c +125c. unless otherwise specified, testing shall be conducted at worst-case conditions. 2. v il = ?3.0v for pulse widths less than or equal to 20ns. 3. duration of the short should not exceed one second; only one output may be shorted at a time. v oh output high level voltage v ol output low level voltage
page 4 of 24 pace1750a document # micro-3 rev. c min max min max min max min max t c(br)l bus req 45 33 25 22 ns t c(br)h bus req 45 33 25 22 ns t bgv(c) bus gnt setup 5555ns t c(bg)x bus gnt hold 5555ns t c(bb)l bus busy low 35 25 24 20 ns t c(bb)h bus busy high 35 25 20 15 ns t bbv(c) bus busy setup 5555ns t c(bb)x bus busy hold 5555ns t c(bl)l bus lock low 50 30 25 21 ns t c(bl)h bus lock high 50 30 25 17 ns t blv(c) bus lock setup 5555ns t c(bl)x (in) bus lock hold 5555ns t c(st )v m/ io , r/ w status 45 30 25 20 ns t c(st )v as 0 -as 3 , ak 0 -ak 3 , d/i status 40 25 20 20 ns t c(st )x as 0 -as 3 , ak 0 -ak 3 , d/i status, m/ io , r/ w 0000ns t c(sa)h strba high 25 22 17 16 ns t c(sa)l strba low 25 22 17 16 ns t sal(iba)x address hold from strba low 5555ns t rav(c) rdya setup 5555ns t c(ra)x rdya hold 5555ns t c(sdw)l strbd low write 25 22 17 14 ns t c(sd)h strbd high 25 22 17 14 ns t fc(sdr)l strbd low read 25 22 17 14 ns t sdrh(ibd)x strbd high 0000ns t sdwh(ibd)x strbd high 45 30 25 17 ns t sdl(sd)h strbd write 50 40 35 20 ns t rdv(c) rdyd setup 5555ns t c(rd)x rdyd hold 5555ns t c(iba)v ib 0 -ib 15 45 30 25 20 ns t fc(iba)x ib 0 -ib 15 0000ns t ibdrv(c) ib 0 -ib 15 setup 5555ns t c(ibd)x ib 0 -ib 15 hold (read) 8765ns t c(ibd)x data valid out (write) 0000ns 40 mhz unit signal propagation delays 1,2 symbol parameter 20 mhz 30 mhz 15 mhz
page 5 of 24 pace1750a document # micro-3 rev. c notes 1. 4.5v v cc 5.5v, ?55c t c +125c. unless otherwise specified, testing shall be conducted at worst-case conditions. 2. all timing parameters are composed of three elements. the first "t" stands for timing. the second represents the "from" sig nal. the third in parentheses indicates "to" signal. when the cpu clock is one of the signal elements, either the rising edge "c" or the falling edge "fc" is referenced. when other elements are used, an additional suffix indicates the final logic level of the signal. "l" - low level, "h" - high level, "v" - valid, "z" - high impedance, "x" - don't care, "lh" - low to high, "zh" - high impedance to high, "r" - read cycle, and "w" - write cycle. min max min max min max min max t fc(ibd)v ib 0 -ib 15 45 30 25 20 ns t c(snw) snew 45 30 26 22 ns t fc(t go) trigo rst 45 30 26 22 ns t rst l(dma enl) dma enable 45 40 35 30 ns t c(dme) dma enable 45 40 35 30 ns t fc(npu) normal power up 45 40 35 30 ns t c(er) clock to major error unrecoverable 75 60 50 45 ns t rst l(npu) reset 65 50 40 30 ns t reqv(c) console request 0000ns t c(req)x console request 10 10 10 10 ns t fv(bb)h level sensitive faults 5555ns t bbh(f)x level sensitive faults 5555ns t irv(c) iol 1-2 int user interrupt (0-5) 0000ns t c(ir)x power down interrupt level sensitive hold 10 10 10 10 ns t rst l (t rst h ) reset pulse width 30 25 20 15 ns t c(xx)z clock to three-state 30 22 17 13 ns t f(f) , t 1(1) edge sensitiive pulse width 5555ns t r , t f clock rise and fall 5555ns 40 mhz unit signal propagation delays 1,2 (continued) symbol parameter 20 mhz 30 mhz 15 mhz
page 6 of 24 pace1750a document # micro-3 rev. c minimum write bus cycle timing diagram note: all time measurements on active signals relate to the 1.5 volt level.
page 7 of 24 pace1750a document # micro-3 rev. c minimum read bus cycle timing diagram note: all time measurements on active signals relate to the 1.5 volt level.
page 8 of 24 pace1750a document # micro-3 rev. c minimum write bus cycle, followed by a non-bus cycle, timing diagram note: all time measurements on active signals relate to the 1.5 volt level.
page 9 of 24 pace1750a document # micro-3 rev. c trigo rst discrete timing diagram note: all time measurements on active signals relate to the 1.5 volt level. normal power up discrete timing diagram dma en discrete timing diagram xio operations snew discrete timing diagram
page 10 of 24 pace1750a document # micro-3 rev. c external faults and interrupts timing diagram edge-sensitive interrupts and faults (sysflt 0 , sysflt 1 ) min. pulse width level-sensitive interrupts note: tc(ir) x max = 35 clocks level-sensitive faults con req note: all time measurements on active signals relate to the 1.5 volt level.
page 11 of 24 pace1750a document # micro-3 rev. c parameter v0 vmea t plz 3v 0.5v t phz 0v v cc ? 0.5v t pxl v cc /2 1.5v t pxh v cc /2 1.5v bus acquisition note: a cpu contending for the bus will assert the bus req line, and will acquire it when bus gnt is assserted and the bus is not locked ( bus lock is high). switching time test circuits standard output (non-three-state) three-state note: all time measurements on active signals relate to the 1.5 volt level.
page 12 of 24 pace1750a document # micro-3 rev. c signal descriptions clocks and external requests mnemonic name description cpu clk cpu clock a single phase input clock signal (0-40 mhz, 40 percent to 60 percent duty cycle. timer clk timer clock a 100 khz input that, after synchronization with cpu clk, provides the clock for timer a and timer b. if timers are used, the cpu clk signal frequency must be > 300 khz. reset reset an active low input that initializes the device. con req console request an active low input that initiates console operations after completion of the current instruction. interrupt inputs mnemonic name description pwrdn int power down interrupt an interrupt request input that cannot be masked or disabled. this signal is active on the positive going edge or the high level, according to the interrupt mode bit in the configuration register. usr 0 int - user interrupt interrupt request input signals that are active on the positive going edge usr 5 int or the high level, according to the interrupt mode bit in the configuration register. iol 1 int - i/o level interrupts active high interrupt request inputs that can be used to expand the iol 2 int number of user interrupts. faults mnemonic name description mem prt er memory protect error an active low input generated by the mmu or bpu, or both and sampled by the bus busy signal into the fault register (bit 0 cpu bus cycle, bit 1 if non-cpu bus cycle). mem par er memory parity error an active low input sampled by the bus busy signal into bit 2 of the fault register. ext adr er external address error an active low input sampled by the bus busy signal into the fault register (bit 5 or 8), depending on the cycle (memory or i/o). sysflt 0 system fault 0 , asynchronous, positive edge-sensitive inputs that set bit 7 (sysflt 0 ) sysflt 1 system fault 1 , or bits 13 and 15 (sysflt 1 ) in the fault register. error control mnemonic name description unrcv er unrecoverable error an active high output that indicates the occurrence of an error classified as unrecoverable. maj er major error an active high output that indicates the occurrence of an error classified as major.
page 13 of 24 pace1750a document # micro-3 rev. c signal descriptions (continued) bus control mnemonic name description d/ i data or instruction an output signal that indicates whether the current bus cycle access is for data (high) or instruction (low). it is three-state during bus cycles not assigned to the cpu. this line can be used as an additional memory address bit for systems that require separate data and program memory. r/ w read or write an output signal that indicates direction of data flow with respect to the current bus master. a high indicates a read or input operation and a low indicates a write or output operation. the signal is three-state during bus cycles not assigned to the cpu. m/ io memory or i/o an output signal that indicates whether the current bus cycle is memory (high) or i/o (low). this signal is three-state during bus cycles not assigned to the cpu. strba address strobe an active high output that can be used to externally latch the memory or i/o address at the high-to-low transition of the strobe. the signal is three-state during bus cycles not assigned to the cpu. rdya addr ess ready an active high input that can be used to extend the address phase of a bus cycle. when rdya is not active, wait states are inserted by the device to accommodate slower memory or i/o devices. strbd data strobe an active low output that can be used to strobe data in memory and xio cycles. this signal is three-state during bus cycles not assigned to the cpu. rdyd data ready an active high input that extends the data phase of a bus cycle. when rdyd is not active, wait states are inserted by the device to accommodate slower memory or i/o devlces. information bus mnemonic name description ib 0 - ib 15 information bus a bidirectional time-multiplexed address/data bus that is three-state during bus cycles not assigned to the cpu. ib 0 is the most significant bit. status bus mnemonic name description ak 0 - ak 3 access key outputs used to match the access lock in the mmu for memory accesses (a mismatch will cause the mmu to pull the mem prt er signal low), and also indicates processor state (ps). privileged instructions can be executed with ps = 0 only. these signals are three-state during bus cycles not assigned to the cpu. as 0 - as 3 address state outputs that select the page register group in the mmu. it is three-state during bus cycles not assigned to the cpu. [these outputs together with d/ i can be used to expand the device direct addressing space to 4 mbytes, in a nonprotected mode (no mmu)]. however, using this addressing mode may produce situations not specified in mil-std-1750.
page 14 of 24 pace1750a document # micro-3 rev. c signal descriptions (continued) bus arbitration mnemonic name description bus req bus request an active low output that indicates the cpu requires the bus. it becomes inactive when the cpu has acquired the bus and started the bus cycle. bus gnt bus grant an active low input from an external arbiter that indicates the cpu currently has the highest priority bus request. if the bus is not used and not locked, the cpu may begin a bus cycle, commencing with the next cpu clock. a high level will hold the cpu in hi-z state (bz), three- stating the ib bus status lines (d/ i , r/ w , m/ io ), strobes (strba, strbd ), and all the other lines that go three-state when this cpu does not have the bus. bus busy bus busy an active low, bidirectional signal used to establish the beginning and end of a bus cycle. the trailing edge (low-to-high transition) is used for sampling bits into the fault register. it is three-state in bus cycles not assigned to this cpu. however, the cpu monitors the bus busy line for latching non-cpu bus cycle faults into the fault register. bus lock bus lock an active low, bi-directional signal used to lock the bus for successive bus cycles. during non-locked bus cycles, the bus lock signal mimics the bus busy signal. it is three-state during bus cycles not assigned to the cpu. the following instructions will lock the bus: incm, decm, sb, rb, tsb, srm, stub and stlb. discrete control mnemonic name description dma en direct memory an active high output that indicates the dma is enabled. it is access enable disabled when the cpu is initialized (reset) and can be enabled or disabled under program control (i/o commands dmae, dmad). nml pwrup normal power up an active high output that is set when the cpu has successfully completed the built-in self test in the initialization sequence. it can be reset by the i/o command rns. snew start new an active high output that indicates a new instruction is about to start executing in the next cycle. trigo rst trigger-go reset an active low discrete output. this signal can be pulsed low under program control i/o address 400b (hex) and is automatically pulsed during processor initialization.
page 15 of 24 pace1750a document # micro-3 rev. c case outline: pin grid array (case z) terminal terminal terminal terminal terminal terminal number symbol number symbol number symbol b1 v cc l5 dma en d11 as 1 b2 ib 14 k5 con req d10 as 2 c1 ib 13 l6 v cc c11 as 3 c2 ib 12 k6 snew c10 iol 2 int d1 ib 11 l7 bus lock b11 v cc d2 ib 10 k7 bus gnt a10 gnd e1 ib 9 l8 bus busy b10 iol 1 int e2 ib 8 k8 m/ io a9 usr 5 int f1 gnd l9 d/ i b9 usr 4 int f2 ib 7 k9 r/ w a8 usr 3 int g1 ib 6 l10 gnd b8 usr 2 int g2 ib 5 k11 rdyd a7 usr 1 int h1 ib 4 k10 rdya b7 usr 0 int h2 ib 3 j11 bus req a6 pwrdn int j1 ib 2 j10 strbd b6 gnd j2 ib 1 h11 strba a5 maj er k1 ib 0 h10 cpu clk b5 sysflt 1 l2 gnd g11 ak 0 a4 sysflt 0 k2 unrcv er g10 ak 1 b4 ext adr er l3 timer clk f11 ak 2 a3 mem par er k3 nml pwrup f10 ak 3 b3 mem prt er l4 reset e11 gnd a2 ib 15 k4 trigo rst e10 as 0 terminal connections
page 16 of 24 pace1750a document # micro-3 rev. c case outlines: leaded chip carrier with unformed leads (case u) and leaded chip carrier with gull- wing leads (case y) terminal terminal terminal terminal terminal terminal number symbol number symbol number symbol 1 gnd 23 ib 11 46 as 2 2 con req 24 ib 12 47 as 1 3 dma en 25 ib 13 48 as 0 4 trigo rst 26 ib 14 49 gnd 5 reset 27 ib 15 50 ak 3 6 nml pwrup 28 mem prt er 51 ak 2 7 timer clk 29 mem par er 52 vcc 8 unrcv er 30 ext adr er 53 ak 1 9 gnd 31 sysflt 0 54 ak 0 10 ib 0 32 sysflt 1 55 cpu clk 11 ib 1 33 maj er 56 strba 12 ib 2 34 gnd 57 strbd 13 ib 3 35 vcc 58 bus req 14 ib 4 36 pwrdn int 59 rdya 15 ib 5 37 usr 0 int 60 rdyd 16 ib 6 38 usr 1 int 61 r/ w 17 ib 7 39 usr 2 int 62 d/ i 18 gnd 40 usr 3 int 63 m/ io 19 ib 8 41 usr 4 int 64 bus busy 20 ib 9 42 usr 5 int 65 bus gnt 21 vcc 43 iol 1 int 66 bus lock 22 ib 10 44 iol 2 int 67 snew 45 as 3 68 vcc terminal connections
page 17 of 24 pace1750a document # micro-3 rev. c case outlines: dual-in-line (case x) and dual-in-line with gull-wing leads (case t) terminal terminal terminal terminal terminal terminal number symbol number symbol number symbol 1 gnd 23 ib 13 44 as 1 2 con req 24 ib 14 45 as 0 3 dma en 25 ib 15 46 gnd 4 trigo rst 26 mem prt er 47 ak 3 5 reset 27 mem par er 48 ak 2 6 nml pwrup 28 ext adr er 49 ak 1 7 timer clk 29 sysflt 0 50 ak 0 8 unrcv er 30 sysflt 1 51 cpu clk 9ib 0 31 maj er 52 strba 10 ib 1 32 gnd 53 strbd 11 ib 2 33 pwrdn int 54 bus req 12 ib 3 34 usr 0 int 55 rdya 13 ib 4 35 usr 1 int 56 rdyd 14 ib 5 36 usr 2 int 57 r/ w 15 ib 6 37 usr 3 int 58 d/ i 16 ib 7 38 usr 4 int 59 m/ io 17 ib 8 39 usr 5 int 60 bus busy 18 ib 9 40 iol 1 int 61 bus gnt 19 vcc 41 iol 2 int 62 bus lock 20 ib 10 42 as 3 63 snew 21 ib 11 43 as 2 64 vcc 22 ib 12 terminal connections note: for the 30 mhz and 40 mhz devices, pins 19 and 46 are connected as shown. for the 15 mhz and 20 mhz devices, these pins are not internally connected to the die.
page 18 of 24 pace1750a document # micro-3 rev. c ordering information standardized military drawing part number pyramid semiconductor cage number pyramid semiconductor part number 5962-8766501tx 3dtt2 p1750a-15gmb 5962-8766501ux 3dtt2 p1750a-15qlmb 5962-8766501xx 3dtt2 p1750a-15cmb 5962-8766501yx 3dtt2 p1750a-15qgmb 5962-8766501zx 3dtt2 p1750a-15pgmb 5962-8766502tx 3dtt2 p1750a-20gmb 5962-8766502ux 3dtt2 p1750a-20qlmb 5962-8766502xx 3dtt2 p1750a-20cmb 5962-8766502yx 3dtt2 p1750a-20qgmb 5962-8766502zx 3dtt2 p1750a-20pgmb 5962-8766503tx 3dtt2 p1750a-30gmb 5962-8766503ux 3dtt2 P1750A-30QLMB 5962-8766503xx 3dtt2 p1750a-30cmb 5962-8766503yx 3dtt2 p1750a-30qgmb 5962-8766503zx 3dtt2 p1750a-30pgmb 5962-8766504tx 3dtt2 p1750a-40gmb 5962-8766504ux 3dtt2 p1750a-40qlmb 5962-8766504xx 3dtt2 p1750a-40cmb 5962-8766504yx 3dtt2 p1750a-40qgmb 5962-8766504zx 3dtt2 p1750a-40pgmb
page 19 of 24 pace1750a document # micro-3 rev. c case outline x: 64 lead top brazed dip package, straight lead version (ordering code c) notes: 1) dimensions are in inches. 2) metric equivalents are given for general information only. 3) unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. inches mm .002 0.05 .005 0.12 .008 0.20 .010 0.25 .015 0.38 .016 0.40 .018 0.45 .025 0.63 .040 1.01 .050 1.27 .185 4.70 .265 6.73 .470 11.93 .530 13.46 .590 14.98 .620 15.74 .645 16.38 1.550 39.37 1.563 39.70
page 20 of 24 pace1750a document # micro-3 rev. c case outline t: 64 lead top brazed dip package, gullwing lead version (ordering code g) notes: 1) dimensions are in inches. 2) metric equivalents are given for general information only. 3) unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) case t is derived from case x by forming the leads to the shown gullwing configuration. inches mm .001 0.03 .003 0.08 .005 0.12 .008 0.20 .010 0.25 .015 0.38 .016 0.41 .022 0.55 .030 0.76 .040 1.01 .050 1.27 .150 3.81 .470 11.93 .530 13.46 .590 14.98 .620 15.74 .868 22.04 1.663 42.24
page 21 of 24 pace1750a document # micro-3 rev. c case outline u: 68 lead quad pack with straight leads (ordering code ql) notes: 1) dimensions are in inches. 2) metric equivalents are given for general information only. 3) unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner . 5) corners indicated as notched may be either notched or square. inches mm .002 0.05 .004 0.10 .006 0.15 .010 0.25 .012 0.30 .020 0.51 .050 1.27 .100 2.54 .116 2.95 .250 6.40 .560 14.22 .570 14.48 .800 20.32 .955 24.25 1.090 27.69
page 22 of 24 pace1750a document # micro-3 rev. c case outline y: 68 lead quad pack with gullwing leads (ordering code qg) notes: 1) dimensions are in inches. 2) metric equivalents are given for general information only. 3) unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner . 5) corners indicated as notched my be either notched or square (with radius). 6) case y is derived from case u by forming the leads to the shown gullwing configuration. inches mm .004 0.10 .005 0.12 .008 0.20 .010 0.25 .012 0.30 .015 0.38 .016 0.41 .020 0.50 .024 0.60 .040 1.02 .050 1.27 .100 2.54 .115 2.92 .570 14.48 .800 20.32 .955 24.25 1.010 25.65 1.090 27.68
page 23 of 24 pace1750a document # micro-3 rev. c case outline z: 68-pin pin grid array (pga) (ordering code pg) notes: 1) dimensions are in inches. 2) metric equivalents are given for general information only. 3) unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) corners except pin number 1 (ref.) can be either rounded or square. 5) all pins must be on the .100" grid. inches mm .016 0.41 .020 0.50 .040 1.01 .050 1.27 .059 1.49 .060 1.52 .098 2.49 .100 2.54 .120 3.04 .150 3.81 .170 4.32 1.010 25.65 1.089 27.66 1.160 29.46
page 24 of 24 pace1750a document # micro-3 rev. c revisions document number : micro-3 document title : pace1750a cmos 16-bit processor rev. issue date orig. of change description of change orig may-89 rkk new data sheet a jul-04 jdb added pyramid logo b aug-05 jdb re-c reated electronic version c oct-05 jdb altered case outline drawing for case x and case t

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